Dr. Ankush Chattopadhyay

Assistant Professor

Electronics & Communication Engineering | ECE

Academic Information

Ph.D. (Engg.): Jadavpur University, 2021

M.Tech.: Indian Institute of Engineering Science and Technology, Shibpur, 2011


Area of Specialization

Modeling and Characterization of various FETs architectures (DG-FET, FinFET, JL-FET etc.), and it’s applications.




10 years


2 years

Date of Joining


Date of Assign as Prof. / A.P

Network Theory (EC 304)
Digital Signal Processing (EC 504)
CMOS VLSI Design (PE-EC 603C)
Mixed Signal Design (PE-EC 802A)
Analog and Digital Electronics (ESC 301)
Control System LAB (EC 691)
Digital Signal Processing LAB (EC 593)
Mini-Project LAB (EC 681)
Digital System Design LAB (EC 392)
Analog and Digital Electronics LAB (ESC 391)
Project LAB (EC 881)

Journal Publications

  1. Ankush Chattopadhyay, “Modeling of negative capacitance underlap gradedchannel junction accumulation mode junctionless FET in nano-scale regime”, Micro and Nanostructures, vol. 183, no.207756, Impact Factor: 3.1, Jan. 2024, doi:https://doi.org/10.1016/j.micrna.2024.207756 .
  2. Ankush Chattopadhyay, Chayanika Bose, "” Investigation of Core-Shell  Junctionless Gate Stack DG-FET in low power application using Charge Based  Modeling”, Journal of Elec. Materi., vol. 53, pp. 157-170 (14 October 2023), Impact Factor: 2.1, doi: https://doi.org/10.1007/s11664-023-10742-x
  3. Rahul Das, Ankush Chattopadhyay, Manash Chanda, Chandan K. Sarkar, Chayanika Bose, “Analytical Modeling of sensitivity parameters influenced by practically feasible arrangement of bio-molecules in Dielectric Modulated FET biosensor”, Silicon (28thJanuary 2022), Impact Factor: 3.4, doi: https://doi.org/10.1007/s12633-021- 01617-z.
  4. Ankush Chattopadhyay, Chandan K. Sarkar, Chayanika Bose, “Compact Programming language known analytical modeling of underlap gate stack graded channel junction accumulation mode junctionless FET in subthreshold regime”, Superlattices and Microstructures (28thDecember 2021), Impact Factor: 3.22, doi: https://doi.org/10.1016/j.spmi.2021.107110.
  5. M. Goswami, A. Chattopadhyay, C. Bose, “Performance Analysis of Dual Material Junction Accumulation Mode tri gate Junctionless SOI FET: Modeling and Simulation”, Silicon (27thOctober 2021), Impact Factor: 3.4, https://doi.org/10.1007/s12633-021-01483-9.
  6. A. Chattopadhyay, M. Chanda, C. Bose, C. K. Sarkar, “Analytical Modeling of Harmonic Distortions in GAA Junctionless FETs for Reliable Low-Power Applications”, Journal of Elec. Materi. vol. 50, pp. 4606-4618 (25thMay 2021), Impact Factor: 2.1, doi: https://doi.org/10.1007/s11664-021-08999-1.
  7. Ankush Chattopadhyay, Manash Chanda, Chayanika Bose, Chandan K. Sarkar, “Analytical modeling of linearity and intermodulation distortion of 3D gate all around junctionless (GAA – JL) FET”, Superlattices and Microstructures, vol. 150, (5thJanuary 2021), Impact Factor: 3.22, doi:https://doi.org/10.1016/j.spmi.2020.106788.
  8. Ankush Chattopadhyay, Chayanika Bose, Chandan K. Sarkar, “Compact Modeling of Graded N-Channel Independent Gate FET with Underlaps, Spacer and S/D Straggle for Low Power Application” Silicon, vol. 13, pp. 375–387, (13thMarch 2020), Impact Factor: 3.4, doi: https://doi.org/10.1007/s12633-020-00424-2.
  9. Ankush Chattopadhyay, Atanu Kundu, Chandan K. Sarkar, Chayanika Bose, “Two-dimensional modeling of the underlap graded-channel FinFET”, Journal of Computational Electronics, vol. 19, no. 2, pp. 688–699, (13thFebruary 2020), Impact Factor: 2.1, doi: https://doi.org/10.1007/s10825-020-01458-w.
  10. Ankush Chattopadhyay, Rahul Das, Arpan Dasgupta, Atanu Kundu, Chandan K. Sarkar, “A linearity based comparison between symmetric and asymmetric lateral diffusion for a 22 nm Underlapped DG-MOSFET”, Superlattices and Microstructures, vol. 107, pp. 69-82, (10thApril 2017), Impact Factor: 3.22, doi:http://doi.org/10.1016/j.spmi.2017.03.056.
  11. Ankush Chattopadhyay, Arpan Dasgupta, Rahul Das, Atanu Kundu, Chandan K. Sarkar, “Effect of spacer dielectric engineering on Asymmetric Source underlapped Double Gate MOSFET using Gate Stack”, Superlattices and Microstructures, vol. 101, pp. 87-95, (15thNovember 2016), Impact Factor: 3.22, doi: http://doi.org/10.1016/j.spmi.2016.11.024.

Conference Publications

  1. M. Goswami, A. Chattopadhyay and C. Bose, “Influence of High-k Oxide Thickness on Gate Stack DMG Junctionless SOI MOSFET,” 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 193-197, doi: https://doi.org/10.1109/DevIC50843.2021.9455802.
  2. A. Chattopadhyay, A. Pathak and P. Mukherjee, “Impact of Dopant variations on Junctionless Cylindrical Nanowire FETs,” 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 2020, pp. 1-4, doi: https://doi.org/10.1109/VLSIDCS47293.2020.9179876.
  3. A. Chattopadhyay, R. Das, A. Dasgupta, A. Kundu and C. K. Sarkar, “Effect of channel engineering on analog/RF performance of underlapped gatestack DGMOSFET in Sub-20nm regime,” 2017 Devices for Integrated Circuit (DevIC), 2017, pp. 299-302, doi: https://doi.org/10.1109/DEVIC.2017.8073956.
  4. A. Chattopadhyay, A. Dutta, A. Kundu and C. K. Sarkar, “Influence on the analog/RF performance in graded channel Gate Stack DG-MOSFETs,” 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), 2016, pp. 167-169, doi: https://doi.org/10.1109/ICDCSyst.2016.7570653.


Book Chapter

  1. Chattopadhyay A., Bose C., Chandan K.S. (2021) Performance and Circuit Analysis of Independent Gate FinFET. In: Das N.R., Sarkar S. (eds) Computers and Devices for Communication. CODEC 2019. Lecture Notes in Networks and Systems, vol 147. pp 427-433, Springer, Singapore. https://doi.org/10.1007/978- 981-15-8366-7_63.



Life Member: Indian Society for Technical Education.


  1. 5-days online Faculty Development Program on “Introduction to Data Science” organized by NITTTR, Kolkata held from 12th June – 16th June 2023.
  2. 5-days online Faculty Development Program (in house) on “Data Security and IoT” held from 11th – 15th July 2022.
  3. 5-days online Faculty Development Program (in house) on “Effective Teaching and Learning” held from 6th – 8th September, 2021.
  4. 5-days online Faculty Development Program (in house) on “Internet of Things (IoT)” held from December 01, 2020 to December 05, 2020.
  5. 5-day online FDP on the theme “Inculcating Universal Human Values in Technical Education” organized by All India Council for Technical Education (AICTE) from 19 April, 2021 to 23 April, 2021.
  6. AICTE Training And Learning (ATAL) Academy Online FDP on “Sensors Technology” from 2020-8-17 to 2020-8-21 at St. Joseph’s Institute of Technology.
  7. AICTE Training And Learning (ATAL) Academy Online Elementary FDP on “Nanodevices and Advanced Nanomaterials” from 06/12/2021 to 10/12/2021 at Sikkim Manipal Institute of Technology.