Congratulations Shabnam Parween (Passout Batch 2024), on receiving offer from FLIPKART with a remuneration of 25.7 LPA

Admissions 2024 - 25

Congratulations Shabnam Parween (Passout Batch 2024), on receiving offer from FLIPKART with a remuneration of 25.7 LPA

Dr. Sanchita Saha Ray

Assistant Professor

Information Technology | IT

Academic Information

 

 

Ph.D. (Engg.): Jadavpur University, 2022

M.E.: MAKAUT formally known as WBUT, 2005

B. Tech.: Sikkim Manipal University, formerly Sikkim Manipal University of Health, Medical and Technological Sciences, 2003

 

Area of Specialization

Network Packet processing.

Experience

Research

Teaching

18 Years

Industry

Date of Joining

14-03-2005

Date of Assign as Prof. / A.P

 

Cloud Computing
Computer Organization
Computer Organization
Formal Language & Automata Theory
Bioinformatics
Database Management System Lab
Programming for Problem Solving Lab

Database Management System
Formal Language & Automata Theory
Computer Organization
Computer Architecture
Bioinformatics
Cloud Computing
Microprocessor & Microcontroller
Embedded System

 

Research Interest

1. FPGA Based Embedded Systems Design
2. Network Packet processing
3. High Performance Computing for Biological Sequences
4. High Performance Computer Architecture

Journal Publications

  1. S. Ghosh and S. Saha Ray, “O(N) Memory-free Hardware Architecture for Burrows-Wheeler Transform,” in IEEE Transactions on Computers, vol. 72, no. 7, pp. 2080-2093, 1 July 2023, doi: 10.1109/TC.2022.32262952022.
  2. S. Saha Ray and S. Ghosh, “k-Degree Parallel Comparison-free Hardware Sorter for Complete Sorting,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 5, pp. 1438-1449, May 2023, doi: 10.1109/TCAD.2022.3207689.
  3. S. Saha Ray, D. Adak and S. Ghosh, “Worst Case O(N) Comparison-Free Hardware Sorting Engine,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 10, pp. 3332-3345, Oct. 2022, doi: 10.1109/TCAD.2021.3131554.
  4. S. Saha Ray, S. Ghosh and B. Sardar, “Memory Efficient Hash-Based Longest Prefix Matching Architecture with Zero False +ve and Nearly Zero False −ve Rate for IP Processing,” in IEEE Transactions on Computers, vol. 71, no. 6, pp. 1261-1275, 1 June 2022, doi: 10.1109/TC.2021.3080184.
  5. A. Sarkar, S. Ghosh, S. Saha Ray (2021) A Hardware-Based Memory-Efficient Solution for Pair-Wise Compact Sequence Alignment, IETE Journal of Research, DOI: 10.1080/03772063.2021.1914200.
  6. S. Saha Ray, S. Ghosh, and B. Sardar, “An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup”, Photonic Network Communication, Springer-Verlag New York, Inc., Vol. 32, No. 3 (December 2016), pp. 359-371. doi:10.1007/s11107-016-0674-8.
  7. S. Saha Ray, K. Das and S. Ghosh, “A RAM-Based MAC Table with Two-Tier Security at Layer 2”, IETE Journal of Research, Taylor & Francis, (Online publication Dec. 2015), Vol. 62, No. 4, pp. 435-445, 2016. doi:10.1080/03772063.2015.1117953.
  8. S. Ghosh, S. Saha Ray, “4th Generation Programmable Logic Computing: A Road Map”, IETE Technical Review, Taylor & Francis, 2007, Vol. 24, No. 6, pp. 439-452. doi:10.4103/02564602.10876628.

 

Conference Publications

  1. S. Ghosh, S. Dasgupta and S. Saha Ray, “A Comparison-free Hardware Sorting Engine,” 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019, pp. 586-591, doi: 10.1109/ISVLSI.2019.00110.
  2. S. Saha Ray, S. Singh, C. Sengupta, S. Ghosh and B. Sardar, “A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing,” 2018 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), 2018, pp. 1-6, doi: 10.1109/ANTS.2018.8710130.
  3. S. Ghosh, S. Kesharwani, V. Mishra and S. Saha Ray, “Hybrid trie based approach for longest prefix matching in IP packet processing,” TENCON 2017 – 2017 IEEE Region 10 Conference, Penang, Malaysia, 2017, pp. 1532-1537. doi: 10.1109/TENCON.2017.8228100
  4. S. Saha Ray, A. Banerjee, A. Datta and S. Ghosh, “A memory efficient DNA sequence alignment technique using pointing matrix,” 2016 IEEE Region 10 Conference (TENCON), Singapore, 2016, pp. 3559-3562. doi:10.1109/TENCON.2016.7848720
  5. S. Saha Ray, N. Srivastava and S. Ghosh, “A hardware-based high-throughput DNA sequence alignment scheme,” 2016 IEEE Annual India Conference (INDICON), Bangalore, India, 2016, pp. 1-6. doi:10.1109/INDICON.2016.7838990
  6. S. Saha Ray, S. Ghosh and B. Sardar, “SRAM based longest prefix matching approach for multigigabit IP processing,” 2015 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), Kolkata, 2015, pp. 1-6. doi:10.1109/ANTS.2015.7413624.
  7. S. Ghosh, S. Mandal and S. Saha Ray, “A scalable high-throughput pipeline architecture for DNA sequence alignment,” TENCON 2015 – 2015 IEEE Region 10 Conference, Macao, 2015, pp. 1-6. doi:10.1109/TENCON.2015.7373055.
  8. S. Saha Ray, A. Bhattacharya and S. Ghosh, “A fast range matching architecture with unit storage expansion ratio and high memory utilization using SBiCAM for packet classification,” 2014 Annual IEEE India Conference (INDICON), Pune, 2014, pp. 1-6. doi:10.1109/INDICON.2014.7030357
  9. S. Saha Ray, S. Ghosh and R. Prasad, “Low-cost hierarchical memory-based pipelined architecture for DNA sequence matching,” 2014 Annual IEEE India Conference (INDICON), Pune, 2014, pp. 1-6. doi:10.1109/INDICON.2014.7030681
  10. S. Saha Ray, A. Chatterjee and S. Ghosh, “A novel approach for prefix minimization using Ternary Trie (PMTT) for packet classification,” TENCON 2014 – 2014 IEEE Region 10 Conference, Bangkok, 2014, pp. 1-6. doi:10.1109/TENCON.2014.7022466
  11. S. Ghosh, S. Saha Ray and S. Mandal, “High through-put scalable query processing architecture using STCAM,” 2013 IEEE International Conference on Computational Intelligence and Computing Research, Enathi, 2013, pp. 1-4. doi:10.1109/ICCIC.2013.6724274
  12. S. Saha Ray, A. Chatterjee and S. Ghosh, “A hierarchical high-throughput and low power architecture for longest prefix matching for packet forwarding,” 2013 IEEE International Conference on Computational Intelligence and Computing Research, Enathi, 2013, pp. 1-4. doi:10.1109/ICCIC.2013.6724271
  13. S. Saha Ray and S. Ghosh, “Smart Ternary Content Addressable Memory (STCAM) architecture,” 2012 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), Ramanathapuram, 2012, pp. 434-438. doi:10.1109/ICACCCT.2012.6320817
  14. S. Ghosh, J. Ghosh and S. Saha Ray, “Architecture of Configurable K-Way C-Access Interleaved Memory,” 2011 International Conference on Process Automation, Control and Computing, Coimbatore, 2011, pp. 1-5. doi:10.1109/PACC.2011.5978873
  15. S. Ghosh, S. Saha Ray, “Register Size Programmable Autoconfigured Register Size for RISC Processors”, Proceedings of International Conference on Embedded Systems and VLSI Design (ICVLSI), Chennai, Feb 14-16, 2008, pp 232 – 236.

 

Member: The Institution of Electronics and Telecommunication Engineers (IETE)

Participated

  1. Faculty Development Programme (online) on “Emerging Trends and Challenges in Higher Education and Research”, organized by Prince Shri Venkateshwara Arts & Science College from April 18- 22, 2022.
  2. Five-day Faculty Development Programme (online) Smt. Sanchita Saha Ray on “Inculcating Universal Human Values in Technical Education” organized by All India Council for Technical Education (AICTE) from 19th -23rd April, 2021.
  3. Faculty Development Programme on “Internet of Things (IoT)”, organized by the department of Electronics and Communication, St. Thomas’ College of Engineering & Technology from December 1-5, 2020.
  4. Five-day Faculty Development Programme on Discrete Mathematics & Its Applications, conducted during 13th January – 17th January, 2020 organized by NITTTR, Kolkata.
  5. Two week Faculty Development Programme on Introduction to DBMS, conducted during 8th to 19th January, 2018 organized by NITTTR, Kolkata.
  6. Eight Weeks Faculty Development Programme on Hardware Modelling with Verilog organized by NPTEL during Aug – Oct, 2018, secured 83% and placed among ELITEs. 

Funded Project

  1. Title: Design and Implementation of a Comparison-Free Scalable High-Throughput Hardware Sorting Engine for FPGA-Based Embedded System Applications. Funding Agency: Department of Higher Education, Science & Technology and Biotechnology, Govt. of West Bengal, Role: Co-Investigator in Collaboration with: IIEST, Shibpur.

  1. Best Paper Award for the paper entitled “A Hierarchical High-throughput and Low Power Architecture for Longest Prefix Matching for Packet Forwarding” presented at 2013 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), 26 – 28 Dec. 2013.
  2. Gowri Memorial Award (GMA) for the Best paper on topic of General Interest, “4th Generation Programmable Logic Computing: A Road Map” published in IETE Technical Review, Vol 24 No 6, Nov-Dec 2007.
  3. Received Bronze Medal in ME, Computer Science & Engineering, position: 1st class 3rd in 2005.